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Professional NTSC/PAL Video Decoder with 10-Bit CCIR656 Output ADV7185
Digital Output Formats (20-Bit Wide Bus): YCrCb (4:2:2 or 4:1:1) CCIR601/CCIR656 8-Bit or Extended 10-Bit 0.5 V to 2.0 V p-p Input Range Differential Gain, 0.4% Typ Differential Phase, 0.6o Typ Programmable Video Controls: Peak White/Hue/Brightness/Saturation/Contrast CCIR/Square/4 FSC Pixel Operation APPLICATIONS Projectors Digital TVs DVD-RAM Recorders and Players PDP Displays Video Decoders Hybrid Analog/Digital Set-Top Boxes Professional Equipment (continued on page 9)
FEATURES Analog Video to Digital YCrCb Video Decoder: NTSC-(M/N), PAL-(B/D/G/H/I/M/N) ADV(R)7185 Integrates Two 12-Bit ADCs Clocked from a Single 27 MHz Crystal Dual Video Clocking Schemes: Line-Locked Clock Compatible (LLC) Adaptive Digital Line Length Tracking (ADLLTTM) 3-Line Chroma Comb Filter Real-Time Clock and Status Information Output Integrated AGC (Automatic Gain Control) and Clamping Multiple Programmable Analog Input Formats: CVBS (Composite Video) SVHS (Y/C) YCrCb Component (VESA, MII, SMPTE, and BetaCam) 6 Analog Input Video Channels Real-Time Horizontal and Vertical Scaling Automatic NTSC/PAL Identification Differential Mode Video Input
FUNCTIONAL BLOCK DIAGRAM
P19-P0 PIXEL O/P PORT
ADV7185
ISO REFOUT AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 ANALOG I/P MULTIPLEXING AUTOMATIC GAIN CONTROL (AGC) CLAMP AND DC RESTORE 12-BIT ADC 12-BIT ADC
SHAPING AND NOTCH LPF
PEAKING HPF/LPF
RESAMPLING AND HORIZONTAL SCALING
LUMA DELAY BLOCK FIFO CONTROL BLOCK AND PIXEL OUTPUT FORMATTER
AFF HFF/QCLK AEF DV RD
LUMA ANTIALIAS LPF
SYNC DETECTION
2H LINE MEMORY
27MHz
SUBCARRIER RECOVERY DTO
RESAMPLING AND HORIZONTAL SCALING
CHROMA COMB FILTER
OE GL/CLKIN
SWITCH
CHROMA ANTIALIAS LPF
SHAPING LPF
VIDEO TIMING AND CONTROL BLOCK
27MHz XTAL OSCILLATOR BLOCK
LLC SYNTHESIS WITH LINELOCKED OUTPUT CLOCK I2C-COMPATIBLE INTERFACE PORT
LLC1 LLC2 LLCREF
ELPF
PWRDN
HSYNC FIELD VSYNC HREF
VREF
CLOCK CLOCK RESET
SDATA SCLOCK ALSB
ADLLT is a trademark and ADV is a registered trademark of Analog Devices, Inc.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
ADV7185-SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (each ADC) Accuracy (each ADC) Integral Nonlinearity3 Differential Nonlinearity3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS3 Output High Voltage, VOH Output Low Voltage, VOL High Impedance Leakage Current Output Capacitance VOLTAGE REFERENCE3 Reference Range, VREFOUT POWER REQUIREMENTS Digital Power Supply, VDD Digital IO Power Supply, VDDIO Analog Power Supply, VAA Digital Supply Current, IDD Digital IO Supply Current, IDDIO Analog Supply Current, IAA4 Power-Up Time
3
1
(VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, VDDIO = 3.15 V to 3.5 V, TMIN to TMAX2, unless otherwise noted.)
Max 12 Unit Bits LSB LSB V V A pF V V A pF V V V V mA mA mA Field Test Conditions 12-Bit Range BSL, 2 V Input Captured in a 10-Bit Range 2 V Input Captured in a 10-Bit Range
Min
Typ
0.5
1.0
0.175 0.325 2 -10 0.8 +10 10
VIN = 0.4 V or 2.4 V
2.4 0.4 10 30 2.15 3.2 3.15 4.75 2.2 3.3 3.3 5.0 125 7 150 1 2.25 3.5 3.5 5.25 165 180
ISOURCE = 3.2 mA ISINK = 0.4 mA
IVREFOUT = 0 A
Sleep Mode until Powered Up
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, and VDDIO = 3.15 V to 3.5 V range. 2 Temperature Range T MIN to TMAX = 0C to 70C 3 Guaranteed by characterization. 4 IAA is total analog current taken by AVDD supply pins. Specifications subject to change without notice.
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ADV7185 VIDEO PERFORMANCE SPECIFICATIONS1, 2
Parameter NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity
2
(VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, VDDIO = 3.15 V to 3.5 V, TMIN to TMAX3, unless otherwise noted.)
Max Unit Degree % % dB dB dB Test Conditions CVBS, Comb/No Comb CVBS, Comb/No Comb
Min
Typ 0.4 0.6 0.5
NOISE SPECIFICATIONS2 SNR (Ramp) Analog Front End Channel Crosstalk LOCK TIME AND JITTER SPECIFICATIONS2 Horizontal Lock Time Horizontal Recovery Time Horizontal Lock Range Line Length Variation Over Field HLock Lost Declared
61
63 63 63
CVBS S-Video/YUV, Single-Ended S-Video/YUV, Differential-Ended
50 50 5 1 1 10 20
Lines Lines % % % HSync HSync VSync VSync Hz Lines ns ns
TV/VCR Mode
Vertical Lock Time VLock Lost Declared FSC Subcarrier Lock Range Color Lock Time LLC Clock Jitter (Short Time Jitter) LLC Clock Jitter (Frame Jitter) CHROMA-SPECIFIC SPECIFICATIONS2 Hue Accuracy Color Saturation Accuracy Color Gain Control Range Analog Color Gain Range Digital Color Gain Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA-SPECIFIC SPECIFICATIONS2 Luma Brightness Accuracy Luma Contrast Accuracy
2 1 400 50 1 37
VCR Mode/Surveillance Mode TV Mode TV Mode, Number of Missing HSyncs VCR/Surveillance Mode, Number of Missing HSyncs First Lock into Video Signal All Modes, Number of Missing VSyncs NTSC/PAL HLock to Color Lock Time RMS Clock Jitter RMS Clock Jitter
0.5 0.6 -6 -6 0 0.1 0 0.1 1.0 1.0 +18 +6 12
Degree % dB dB dB % Degree % % %
S-Video, YUV, Overall CGC Range (Analog and Digital) S-Video, YUV CVBS, S-Video, YUV
Video Input Range = 1.0 V p-p Video Input Range = 1.0 V p-p
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, and VDDIO = 3.15 V to 3.5 V range. 2 Guaranteed by characterization. 3 Temperature range T MIN to TMAX = 0C to 70C Specifications subject to change without notice.
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ADV7185 TIMING SPECIFICATIONS
Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency I2C PORT3 SCL Clock Frequency SCL Min Pulsewidth High, t1 SCL Min Pulsewidth Low, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SCL/SDA Rise Time, t6 SCL/SDA Fall Time, t7 Setup Time (Stop Condition), t8 RESET FEATURE Reset Pulse Input Width CLOCK OUTPUTS LLC1 Cycle Time, t9 LLC1 Cycle Time, t9 LLC1 Cycle Time, t9 LLC1 Min Low Period, t10 LLC1 Min High Period, t11 LLC1 Falling to LLCREF Falling, t12 LLC1 Falling to LLCREF Rising, t13 LLC1 Rising to LLC2 Rising, t14 LLC1 Rising to LLC2 Falling, t15 CLKIN Cycle Time, t18 DATA AND CONTROL OUTPUT Data Output Hold Time, t17 Data Output Access Time, t16 Data Output Access Time, t19 Data Output Hold Time, t20 Propagation Delay to High Z, t21 Max Output Enable Access Time, t22 Min Output Enable Access Time, t23 26 30 20 11 5 8 5 33 25 8 11
3
2 1 (VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, VDDIO = 3.15 V to 3.5 V, TMIN to TMAX ,
unless otherwise noted.)
Min Typ 27 0 0.6 1.3 0.6 0.6 100
Max
Unit MHz
Test Conditions
400
300 300 0.6 74 37 33.9 40.8 18 18 4 6 3 1 37
kHz s s s s ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CCIR601 Mode 27 MHz PAL Square Pixel Mode 29.5 MHz NTSC Square Pixel Mode 24.5 MHz CCIR601 Mode 27 MHz CCIR601 Mode 27 MHz
5 3
SCAPI and CAPI Modes LLC Mode LLC Mode SCAPI and CAPI Modes SCAPI and CAPI Modes
6
2
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, and VDDIO = 3.15 V to 3.5 V range. 2 Temperature range T MIN to TMAX = 0C to 70C 3 Guaranteed by characterization. Specifications subject to change without notice.
ANALOG FRONT END SPECIFICATIONS
Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Voltage Clamp Level Clamp Source Current Clamp Sink Current Clamp Source Current Clamp Sink Current Min
2 1 (VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, VDDIO = 3.15 V to 3.5 V, TMIN to TMAX ,
unless otherwise noted.)
Max Unit F M V A A mA mA
Typ 0.1 10 1.4 +3 -3 +0.9 -0.9
Test Conditions
Clamp Switched Off Signal Already Clamped (Fine Clamping) Signal Already Clamped (Fine Clamping) Acquire Mode (Fast Clamping) Acquire Mode (Fast Clamping)
NOTES 1 The max/min specifications are guaranteed over this range. The max/min values are typical over VAA = 4.75 V to 5.25 V, VDD = 3.2 V to 3.5 V, and VDDIO = 3.15 V to 3.5 V range. 2 Temperature range T MIN to TMAX = 0C to 70C Specifications subject to change without notice.
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t3
SDATA
t3
SCLOCK
t6 t1
t5
t8
t2
t7
t4
Figure 1. MPU Port Timing Diagram
t9 t10
LLC1
t11
LLCREF
t12
t13
t14
LLC2
t15
t17
OUTPUTS P0-P19, HREF, VREF, VSYNC, HSYNC, FIELD, DV
t16
Figure 2. LLC Clock, Pixel Port, and Control Outputs Timing Diagram
t18
CLKIN
t20
OUTPUTS P0-P19, HREF, VREF, VSYNC, HSYNC, FIELD, DV
t19
Figure 3. Pixel Port and Control Outputs in CAPI and SCAPI Mode Timing Diagram
OE
t23
OUTPUTS P0-P19, HS, VS, VREF, HREF, FIELD, DV
t21
t22
Figure 4. OE Timing Diagram
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ABSOLUTE MAXIMUM RATINGS 1 ORDERING GUIDE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V VDDIO to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Voltage on Digital Input Pins . . GND - 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 260C Analog Outputs to GND2 . . . . . . . . . . . . GND - 0.5 V to VAA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog output short circuit to any power supply or common can be of an indefinite duration.
Model ADV7185KST
Temperature Range 0C to 70C
Package 80-LQFP
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7185 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATION
HREF/HRESET VREF/VRESET SCLK SDATA
DVDD3
RESET AVSS
DVSS3
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VS/ACTIVE 1 HS/ACTIVE 2 DVSSIO 3 DVDDIO 4 P15 5 P14 6 P13 7 P12 8 DVSS2 9 DVDD2 10 AFF 11 HFF/QCLK/GL 12 AEF 13 DVSSIO 14 DVDDIO 15 CLKIN 16 P11 17 P10 18 P9 19 P8 20
AVSS6
60 AIN5 59 AVSS5 58 AIN4 57 AVSS4 56 AVSS 55 CAPC2 54 CAPC1 53 AVSS 52 CML 51 REFOUT 50 AVDD 49 CAPY2 48 CAPY1 47 AVSS 46 AIN3 45 AVSS3 44 AIN2 43 AVSS2 42 AIN1 41 AVSS1
FIELD
ALSB
PIN 1 IDENTIFIER
ADV7185
TOP VIEW (Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P2 P1
P0
LLCREF
LLC1/PCLK XTAL1
PWRDN ELPF AVDD
LLC2
XTAL
DVDD1 DVSS1
P7 P6
P5
P4
P3
AVSS
AIN6
P16
P17
P18
P19
ISO
OE DV RD
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PIN FUNCTION DESCRIPTIONS
Pin 1
Mnemonic VS/VACTIVE
Input/Output O
Function VS or Vertical Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is an output signal that indicates a vertical sync with respect to the YUV pixel data. The active period of this signal is six lines of video long. The polarity of the VS signal is controlled by the PVS bit. VACTIVE (OM_SEL[1:0] = 1, 0 or 0, 1) is an output signal that is active during the active/viewable period of a video field. The polarity of VACTIVE is controlled by the PVS bit. HS or Horizontal Sync. A dual-function pin, (OM_SEL[1:0] = 0, 0) is a programmable horizontal sync output signal. The rising and falling edges can be controlled by HSB[9:0] and HSE[9:0] in steps of 2 LLC1. The polarity of the HS signal is controlled by the PHS bit. HACTIVE (OM_SEL[1:0] = 1, 0 or 0, 1) is an output signal that is active during the active/viewable period of a video line. The active portion of a video line is programmable on the ADV7185. The polarity of HACTIVE is controlled by PHS bit. Digital I/O Ground Digital I/O Supply Voltage (3.3 V) Video Pixel Output Port. 8-bit multiplexed YCrCb pixel port (P19-P12); 16-bit YCrCb pixel port (P19-P12 = Y and P9-P2 = Cb,Cr); 10-bit multiplexed extended YCrCb pixel port (P19-P10); and 20-bit YCrCb pixel port (P19-P0). P0 represents the LSB. P1-P0 can also be configured as gPO [1] and gPO [0], and P11-P10 can be configured as gPO [3] and gPO [2] respectively. Ground for Digital Supply Digital Supply Voltage (3.3 V) Almost Full Flag. A FIFO control signal indicating when the FIFO has reached the almost full margin set by the user (use FFM[4:0]). The polarity of this signal is controlled by the PFF bit. Half Full Flag. A multifunction pin (OM_SEL[1:0] = 1, 0), it is a FIFO control signal that indicates when the FIFO is half full. The QCLK (OM_SEL[1:0] = 0, 1) pin function is a qualified pixel output clock when using FIFO SCAPI mode. The GL (OM_SEL[1:0] = 0, 0) function (Genlock output) is a signal that contains a serial stream of data that contains information for locking the subcarrier frequency. The polarity of HFF signal is controlled by the PFF bit. Almost Empty Flag. A FIFO control signal, it indicates when the FIFO has reached the almost empty margin set by the user (use FFM[4:0]). The polarity of this signal is controlled by the PFF bit. Asynchronous FIFO Clock. This asynchronous clock is used to output data onto the P19-P0 bus and other control signals. Clock Reference Output. This is a clock qualifier distributed by the internal CGC for a data rate of LLC2. The polarity of LLCREF is controlled by the PLLCREF bit. Line-Locked Clock System Output Clock/2 (13.5 MHz) Line-Locked Clock System Output Clock. A dual-function pin (27 MHz 5%) or a FIFO output clock ranging from 20 MHz to 35 MHz. Second terminal for crystal oscillator; not connected if external clock source is used. Input terminal for 27 MHz crystal oscillator or connection for external oscillator with CMOS-compatible square wave clock signal Power-Down Enable. A logical low will the place part in a power-down status. This pin is used for the External Loop Filter that is required for the LLC PLL. Analog Supply Voltage (+5 V)
2
HS/HACTIVE
O
3, 14 4, 15 5-8, 17-24, 32-35, 73-76
DVSSIO DVDDIO P19-P0
G P O
9, 31, 71 10, 30, 72 11
DVSS1-DVSS3 DVDD1-DVDD3 AFF
G P O
12
HFF/QCLK/GL
I/O
13
AEF
O
16 25
CLKIN LLCREF
I O
26 27 28 29 36 37 38
LLC2 LLC1/PCLK XTAL1 XTAL PWRDN ELPF AVDD
O O O I I P G
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PIN FUNCTION DESCRIPTIONS (continued)
Pin 39, 40, 47, 53, 56, 63 41, 43, 45, 57, 59, 61 42, 44, 46, 58, 60, 62 48, 49 50 51 52 54, 55 64 65
Mnemonic AVSS AVSS1-AVSS6 AIN1-AIN6 CAPY1-CAPY2 AVDD REFOUT CML CAPC1-CAPC2 RESET ISO
Input/Output G G I I P O O I I I
Function Ground for Analog Supply Analog Input Channels. Ground if single-ended mode is selected. These pins should be connected directly to REFOUT when differential mode is selected. Video Analog Input Channels ADC Capacitor Network Analog Supply Voltage (5 V) Internal Voltage Reference Output Common-Mode Level for ADC ADC Capacitor Network System Reset Input. Active Low Input Switch Over. A low to high transition on this input indicates to the decoder core that the input video source has been changed externally and configures the decoder to reacquire the new timing information of the new source. This is useful in applications where external video muxes are used. This input gives the advantage of faster locking to the external muxed video sources. A low to high transition triggers this input. TTL Address Input. Selects the MPU address: MPU address = 88h ALSB = 0, disables I2C filter MPU address = 8Ah ALSB = 1, enables I2C filter MPU Port Serial Data Input/Output MPU Port Serial Interface Clock Input VREF or Vertical Reference Output Signal. Indicates start of next field. VRESET or Vertical Reset Output is a signal that indicates the beginning of a new field. In SCAPI/CAPI mode this signal is one clock wide and active low relative to CLKIN. It immediately follows the HRESET pixel, and indicates that the next active pixel is the first active pixel of the next field. HREF or Horizontal Reference Output Signal. A dual-function pin (enabled when Line-Locked Interface is selected, OM_SEL[1:0] = 0,0), this signal is used to indicate data on the YUV output. The positive slope indicates the beginning of a new active line, HREF is always 720 Y samples long. HRESET or Horizontal Reset Output (enabled when SCAPI or CAPI is selected, OM_SEL[1:0] = 0, 1 or 1, 0) is a signal that indicates the beginning of a new line of video. In SCAPI/CAPI this signal is one clock cycle wide and is output relative to CLKIN. It immediately follows the last active pixel of a line. The polarity is controlled via PHVR. Asynchronous FIFO Read Enable Signal. A logical high on this pin enables a read from the output of the FIFO. DV or Data Valid Output Signal. In SCAPI/CAPI mode, DV performs two functions, depending on whether SCAPI or CAPI is selected. It toggles high when the FIFO has reached the AFF margin set by the user, and remains high until the FIFO is empty. The alternative mode is where it can be used to control FIFO reads for bursting information out of the FIFO. In API mode DV indicates valid data in the FIFO, which includes both pixel information and control codes. The polarity of this pin is controlled via PDV. Output Enable Controls Pixel Port Outputs. A logic high will three-state P19-P0. ODD/EVEN Field Output Signal. An active state indicates that an even field is being digitized. The polarity of this signal is controlled by the PF bit.
66
ALSB
I
67 68 69
SDATA SCLOCK VREF/VRESET
I/O I O
70
HREF/HRESET
O
77 78
RD DV
I O
79 80
OE FIELD
I O
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(FEATURES continued from page 1) Simplified Digital Interface On-Board Digital FIFO Optimized Programmable Video Source Modes: Broadcast TV VCR/Camcorder Security/Surveillance Integrated On-Chip Video Timing Generator Synchronous or Asynchronous Output Timing Line-Locked Clock Output Closed Captioning Passthrough Operation Vertical Blanking Interval Support Power-Down Mode 2-Wire Serial MPU Interface (I2C-Compatible) 5 V Analog 3.3 V Digital Supply Operation 80-Lead LQFP Package
ANALOG INPUT PROCESSING
The ADV7185 has six analog video input channels. These six channels can be arranged in a variety of configurations to support up to six CVBS input signals, three S-video input signals and two YCrCb component analog video input signals. The INSEL[3:0] bits control the input type and channel selected. The analog front end includes three clamp circuits for dc restore. There are three sample-and-hold amplifiers prior to the ADC that are used to enable simultaneous sampling of up to three channels in a YCrCb input mode. Two 12-bit ADCs are used for sampling. The entire analog front end is fully differential which ensures that the video is captured to the highest quality possible. This is very important in highly integrated systems such as video decoders. Figure 5 shows the analog front end section of the ADV7185.
MUX 6CVBS 3YC 2YUV
GENERAL DESCRIPTION
The ADV7185 is an integrated video decoder that automatically detects and converts a standard analog baseband television signal compatible with worldwide standards NTSC or PAL into 4:2:2 or 4:1:1 component video data compatible with 16-/8-bit CCIR601/CCIR656 or 10-/20-bit extended standards. The advanced and highly flexible digital output interface enables performance video decoding and conversion in both frame-buffer-based and line-locked, clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional systems. Fully integrated line stores enable real-time horizontal and vertical scaling of captured video down to icon size. The 12-bit accurate A/D conversion provides professional quality SNR performance. This allows true 8-bit resolution in the 8-bit output mode, and broadcast quality in the 10-bit extended mode. The six analog input channels accept standard composite or advanced component video including S-video and YCrCb video signals in an extensive number of combinations. AGC and clamp restore circuitry allow an input video signal peakto-peak range of 0.5 V up to 2 V. Alternatively, these can be bypassed for manual settings. The fixed 27 MHz clocking of the ADCs and data path for all modes allows very precise and accurate sampling and digital filtering. The line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line-locked even with 5% line length variation. The output control signals allow glueless interface connection in almost any application. The ADV7185 modes are set up over a 2-wire serial bidirectional port (I2C-compatible). The ADV7185 is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7185 is packaged in a small 80-pin LQFP package.
CLAMP V1
CLAMP U1
CLAMP Y1
SHA 2
SHA 2
SHA 2
12 MUX Y ADC2 12 C ADC2
NOTES ANALOG SIGNAL PATH KEPT FULLY DIFFERENTIAL ADCs: 12-BIT ACCURATE; 12dB GAIN RANGE 1CLAMP BLOCKS CONTAIN A SET OF CURRENT SOURCES FOR DC RESTORATION; U AND V HAVE ONLY HALF BANDWIDTH (SAMPLED SIMULTANEOUSLY, CONVERTED SEQUENTIALLY) 2PIPELINED
Figure 5. Analog Front End Block Diagram
CLAMPING
The clamp control on the ADV7185 consists of a digitally controlled analog current and voltage clamp and a digitally controlled digital clamp circuit. The coupling capacitor on each channel is used to store and filter the clamping voltage. A digital controller controls the clamp up and down current sources that charge the capacitor on every line. Four current sources are used in the current clamp control, two large current sources are used for coarse clamping, and two small current sources are used for fine clamping. The voltage clamp, if enabled, is only used on startup or if a channel is switched; this clamp pulls the video into the midrange of the ADC, which results in faster clamping and faster lock-in time for the decoder. The fourth clamp controller is fully digital and clamps the ADC output data, which results in extremely accurate clamping. It also has the added advantage of being fully digital, which results in very fast clamp timing and makes the entire clamping process very robust in terms of handling large amounts of hum that can be present on real-world video signals. In S-video mode there are two clamp controllers used to separately control the luminance clamping and the chrominance
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clamping. Also, in YCrCb component input mode there are two clamp controllers used to control the luminance clamping and the CrCb clamping separately; there are, however, individual current clamps on the Cr and Cb inputs. User programmability is built into the clamp controllers which enable the current and digital clamp controllers to be set up to user-defined conditions. Refer to analog clamp control register (14h), digital clamp control register (15h), and digital color clamp offset register (15h and 16h) for control settings.
ANALOG-TO-DIGITAL CONVERTERS
ANALOG INPUT LEVEL 2V p-p - dB
this mode when white peak mode is detected. White peak mode is activated when the input video exceeds the maximum luminance range for long periods; this mode is designed to prevent clipping of the input video signal. 6. Based on the active video peak white. PW_UPD sets the gain update frequency (once per video per field). 7. Based on the average active video. PW_RES sets what lines are used, only relevant if the signal conforms to PAL 625 line standard. 8. The luminance channel gain is frozen at its present value.
MAXIMUM 6
Two 12-bit ADCs are used in the ADV7185, and they run from a 27 MHz input clock. An integrated band gap generates the required reference voltages for the converters. If the decoder is configured in CVBS mode, the second ADC can be switched off to reduce power consumption; see PSC[1:0].
AUTOMATIC GAIN CONTROL
0 RANGE = 12dB 0
The AGC control block on the ADV7185 is a digitally based system. This controller ensures that the input video signal (CVBS, S-video, or YCrCb) is scaled to its correct value such that the YCrCb digital output data matches the correct gain of the video signal. The AGC has an analog input video range of 0.5 V p-p to 2.0 V p-p, which gives a -6 dB to +6 dB gain range. Figure 6 demonstrates this range. This AGC range will compensate for video signals that have been incorrectly terminated or have been attenuated due to cable loss, or other factors. There are two main control blocks: one for the luminance channel and one for the chrominance channel. The luminance automatic gain control has eight modes of operation: 1. Manual AGC mode where gain for luminance path is set manually using LGM[11:0]. 2. Blank level to sync tip is used to set luminance gain; manual MIRE[2:0] controls the maximum value through luminance channel. There is no override of this mode when white peak mode is detected. 3. Blank level to sync tip is used to set luminance gain; manual MIRE[2:0] controls the maximum value through luminance channel. There is override of this mode when white peak mode is detected. White peak mode is activated when the input video exceeds the maximum luminance range for long periods, this mode is designed to prevent clipping of the input video signal. 4. Blank level to sync tip is used to set luminance gain; MIRE[2:0] is automatically controlled to set the maximum value through the luminance channel. There is no override of this mode when white peak mode is detected. 5. Blank level to sync tip is used to set luminance gain; manual MIRE[2:0] is automatically controlled to set the maximum value through the luminance channel. There is override of
-6 MINIMUM
Figure 6. Analog Input Range
The chrominance automatic gain control has four modes of operation: 1. Manual AGC mode where gain for chrominance path is set manually using CGM[11:0]. 2. Luminance gain used for chrominance channel. 3. Chrominance automatic gain based on color burst amplitude. 4. Chrominance gain frozen at its present setting. Both the luminance and chrominance AGC controllers have a programmable time constant that allows the AGC to operate in four modes: slow, medium, fast, and video quality controlled. The maximum IRE (MIRE[2:0]) control can be used to set the maximum input video range that can be decoded. Table I shows the selectable range.
Table I. MIRE Control
MIRE[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Function PAL (IRE) NTSC (IRE) 133 125 120 115 110 105 100 100 122 115 110 105 100 100 100 100
-10-
REV. 0
CONTROLLED ADC INPUT LEVEL - dB
ADV7185
LUMINANCE PROCESSING
0
ATTENUATION - dB
Figure 7 shows the luminance data path. The 12-bit data from the Y ADC is applied to an antialiasing low-pass filter that is designed to band-limit the input video signal such that aliasing does not occur. This filter dramatically reduces the design on an external analog antialiasing filter; this filter need only remove components in the input video signal above 22 MHz. The data then passes through a shaping or notch filter. When in CVBS mode, a notch filter must be used to remove the unwanted chrominance data that lies around the subcarrier frequency. A wide variety of programmable notch filters for both PAL and NTSC are available. The YSFM[4:0] control the selection of these filters; refer to Figures 8 and 9 for plots of these filters. If S-video or component mode is selected a notch filter is not required. The ADV7185 offers 18 possible shaping filters (SVHS1-18) with a range of low-pass filter responses from 0.5 MHz up to 5.75 MHz. The YSFM[4:0] control the selection of these filters. Please refer to Figures 8 through 16 for filter plots. The next stage in the luminance processing path is a peaking filter. This filter offers a sharpness function on the luminance path. The degree of sharpness can be selected using YPM[2:0]. If no sharpness is required, this filter can be bypassed. The luminance data is then passed through a resampler to correct for line length variations in the input video. This resampler is designed to always output 720 pixels per line for standard PAL or NTSC. The resampler used on the ADV7185 is of very high quality as it uses 128 phases to resample the video, giving 1/128 pixel resolution. The resampler is controlled by a sync detection block that calculates line length variations on the input video. The final stage in the luminance path, before it is applied to an output formatter block, is a 2-line delay store that is used to compensate for delays in the chroma datapath when chroma comb filter is selected.
ANTIALIASING LPF SYNC DETECTION
-10
-20
-30
-40
SVHS1 SVHS2 SVHS17 SVHS3 SVHS18 SVHS4 SVHS5 SVHS6 SVHS7 SVHS8 SVHS9 SVHS10 SVHS11 SVHS12 SVHS13 SVHS14 SVHS15 SVHS16
-50
-60
0
1
2
3 4 5 FREQUENCY - MHz
6
7
8
Figure 8. Luminance SVHS1-SVHS18 Shaping Filter Responses
1.0 0.8 0.6 ATTENUATION - dB 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1 2 3 4 FREQUENCY - MHz 5 6
Figure 9. Luminance SVHS1-SVHS18 Shaping Filter Responses (Close-Up)
ADC DATA
0
SHAPING AND NOTCH FILTER
PEAKING FILTER
RESAMPLE
-10
ATTENUATION - dB
NTSC WN1 NTSC WN2 NTSC WN3 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN2 NTSC NN3 NTSC WN1 NTSC NN2 NTSC NN1 NTSC WN3
-20
Y DELAY LINE STORES
-30
-40
Figure 7. Luminance Processing Path
-50
-60
0
1
2
3 4 5 FREQUENCY - MHz
6
7
8
Figure 10. Luminance NTSC Narrow/Wide Notch Shaping Filter
REV. 0
-11-
ADV7185
1.0 0.8 0.6 ATTENUATION - dB 10 8 6 PS2 PS1
ATTENUATION - dB
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY - MHz 3.0 NTSC WN1 NTSC WN2 NTSC WN3 NTSC NN1 NTSC NN2 NTSC NN3
4 2 0 -2
PS3
PS4
PS5 -4 -6 -8 0 1 2
PS6 3 4 FREQUENCY - MHz 5 6 7
3.5
4.0
Figure 11. Luminance NTSC Narrow/Wide Notch Shaping Filter (Close-Up)
Figure 14. Luminance Peaking Filter Responses in S-Video (SVHS17 Selected)
0 PAL NN1 PAL NN2 PAL NN3 PAL W1 PAL W2 PAL NN3 PAL W1 PAL W2 PAL NN2
6 4 2
ATTENUATION - dB
PC1
-10
ATTENUATION - dB
-20 PAL NN1 -30
PC2 0 -2 -4 -6 PC3 PC4 PC5 PC6
-40
-50
-8
-60
0
1
2
3 4 5 FREQUENCY - MHz
6
7
8
-10
0
1
2
3 4 FREQUENCY - MHz
5
6
7
Figure 12. Luminance PAL Narrow/Wide Notch Shaping Filter Responses
Figure 15. Luminance Peaking Filter Responses in CVBS (PAL NN3 Selected)
1.0 0.8
6 PC1 4
0.6 ATTENUATION - dB
ATTENUATION - dB
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 0.5 1.0 PAL NN1 PAL NN2 PAL NN3 PAL WN1 PAL WN2
2 PC2 0 PC3 PC4 -2 PC5 PC6 -4
-6 -8
1.5 2.0 2.5 FREQUENCY - MHz
3.0
3.5
4.0
0
1
2 3 4 FREQUENCY - MHz
5
6
Figure 13. Luminance PAL Narrow/Wide Notch Shaping Filter Responses (Close-Up)
Figure 16. Luminance Peaking Filter Responses in CVBS (NTSC NN3 Selected)
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REV. 0
ADV7185
CHROMINANCE PROCESSING
0
Figure 17 shows the chrominance data path. The 12-bit data from the Y ADC (CVBS mode) or the C ADC (S-video) is first demodulated. The demodulation is achieved by multiplying by the locally generated quadrature subcarrier, where the sign of the cos subcarrier is inverted from line to line according to the PAL switch, and then low-pass filtering is applied to removed components at twice the subcarrier frequency. For NTSC, the phase of the locally generated subcarrier during color burst is the same as the phase of the color burst. For PAL, the phase of the color burst changes from line to line, relative to the phase during active video, and the phase of the locally generated subcarrier is the average of these two values. The chrominance data is then passed through an antialiasing filter, which is a band-pass filter to remove the unwanted luminance data. This antialiasing filter dramatically reduces the external antialiasing filter requirements as it has only to filter components above 25 MHz. In component mode, the demodulation block is bypassed. The next stage of processing is a shaping filter that can be used to limit the chrominance bandwidth to between 0.5 MHz and 3 MHz; the CSFM[2:0] can be used to select these responses. It should be noted that in CVBS mode, a filter of no greater than 1.5 MHz should be selected as CVBS video is typically band-limited to below 1.5 MHz. In S-video mode, a filter of up to 2 MHz can be used. In component mode, a filter of up to 3 MHz can be used as component video has higher bandwidth than CVBS or S-video. The chrominance data is then passed through a resampler to correct for line length variations in the input video. This resampler is designed to always output 720 pixels per line for standard PAL or NTSC. The resampler used on the ADV7185 is of very high quality as it uses 64 phases to resample the video, giving 1/64 pixel resolution. The resampler is controlled by a sync detection block that calculates line length variations on the input video. The final stage in the chrominance path, before it is applied to an output formatter block, is chroma comb filter.
SINE ANTIALIASING LPF CV/C 27MHz COSINE ANTIALIASING LPF 13.5MHz
-10
ATTENUATION - dB
-20 SH1 -30 SH2 SH3 SH4 SH5 SH6
-40
-50
-60
0
0.5
1.0
1.5 2.0 2.5 FREQUENCY - MHz
3.0
3.5
4.0
Figure 18. Chrominance Shaping Filter Responses
1.0 0.8 0.6 ATTENUATION - dB 0.4 0.2 0 -0.2 -0.4 SH1 -0.6 -0.8 -1.0 0 0.5 1.0 1.5 2.0 2.5 FREQUENCY - MHz 3.0 3.5 4.0 SH2 SH3 SH4 SH5 SH6
Figure 19. Chrominance Shaping Filter Responses (Close-Up)
SHAPING LPF
6.75MHz
13.5MHz
SUBCARRIER RECOVERY
SYNC DETECTION
RESAMPLE
U/V CHROMA COMB FILTERS
Figure 17. Chrominance Processing Path
REV. 0
-13-
ADV7185
OUTPUT INTERFACE Mode Selection Overview
The ADV7185 supports three output interfaces: LLC-compatible synchronous pixel interface, the CAPI interface, and SCAPI interface. When the part is configured in the synchronous pixel interface mode, pixel and control data are output synchronous with LLC1 (8-bit or 10-bit mode) or LLC2 (16-bit or 20-bit mode). In this mode, control and timing information for field, vertical blanking, and horizontal blanking identification may also be encoded as control codes. When configured in CAPI or SCAPI mode, only the active pixel data is output synchronous with the CLKIN (asynchronous FIFO clock). The pixels are output via a 512-pixel deep 20-bit wide FIFO. HACTIVE and VACTIVE are output on independent pins. HACTIVE will be active during the active viewable period of a video line and VACTIVE will be active during the active viewable period of a video field. CAPI and SCAPI modes will
always output data in 16-bit or 20-bit mode, so this mode of operation cannot be used when an 8-bit or 10-bit output interface is required. After power-up, the ADV7185 will default to the LLC-compatible 8-bit CCIR656 4:2:2 @ LLC.
Synchronous Pixel Interface
When the output is configured for an 8-bit pixel interface, the data is output on the pixel output port P[12:19]; 10-bit pixel interface uses P[13:19]. In this mode, 10/8 bits of chrominance data will precede 8/10 bits of luminance data. New pixel data is output on the pixel port after each rising edge of LLC1. When the output is configured for a 16-bit pixel interface, the luminance data is output on P[19:12] and the chrominance data on P[2:9]. In this mode the data is output with respect to LLC2. 20-bit pixel operation will use P[19:10] for luminance data and P[9:0] for chrominance data; as with the 16-bit mode data is output with respect to LLC2. Figure 20 shows the basic timing relationship for this mode.
LLC1
LLC2
PIXEL DATA P[19-12][7:0]
SAV 00
SAV XY
Y0
Y1
Y2
Y3
Y4
PIXEL DATA P[9-2][7:0]
SAV FF
00
SAV
Cb0
Cr0
Cb1
Cr1
Cb2
Figure 20. Synchronous Pixel Interface, 16-Bit Example
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REV. 0
ADV7185
CVBS INPUT
HREF DV
VREF VSYNC FIELD SAV/EAV V BIT
SAV/EAV H BIT SAV/EAV F BIT
Figure 21. NTSC End Even Field (LLC Mode)
CVBS INPUT
HREF DV
VREF VSYNC FIELD SAV/EAV V BIT
SAV/EAV H BIT SAV/EAV F BIT
Figure 22. NTSC End Odd Field (LLC Mode)
REV. 0
-15-
ADV7185
CVBS INPUT
HREF DV
VREF VSYNC FIELD SAV/EAV V BIT
SAV/EAV H BIT SAV/EAV F BIT
Figure 23. PAL End Even Field (LLC Mode)
CVBS INPUT
HREF DV
VREF VSYNC FIELD SAV/EAV V BIT
SAV/EAV H BIT SAV/EAV F BIT
Figure 24. PAL End Odd Field (LLC Mode)
-16-
REV. 0
ADV7185
Control and Pixel Interface FIFO Modes
When the ADV7185 is configured to operate in this mode, pixel data generated within the part is buffered by a 512-pixel deep FIFO. Only active video pixels and control codes are written into the FIFO; the others have been dropped. In this mode, the output is operating asynchronously and a CLKIN must be provided to clock pixels out of the FIFO. The CLKIN must operate faster than the effective data transfer rate into the FIFO. This rate will be determined by the number of active pixels per line. If the CLKIN is not above this, the FIFO may overflow. The ADV7185 controls the FIFO when set to operate in SCAPI mode. DV (data valid) is internally fed back to the RD (read enable), unlike the synchronous pixel mode where DV will not indicate the validity of the current pixel and only acts as an indication of how much data is stored in the FIFO. DV will go high at the same time as AFF and remain high until the FIFO is empty.
By internally setting DV to RD, the system ensures that the FIFO never overflows. When using this mode, the status of data on the pixel outputs can be determined by two indicators, DV and QCLK. DV will go active two clock cycles (LLC1) before valid data appears on the bus. QCLK is a qualified clock derived from CLKIN, but will only be present when valid pixel data is output from the FIFO. DV indicates valid pixel or control code data. Using these two control signals, the user can differentiate between pixel information and invalid data. Figure 25 shows the basic timing relationship for this mode. The operation of the ADV7185 in CAPI mode is similar to that of SCAPI mode with the exception that now the FIFO is controlled by the system; the system must monitor the almost full flag (AFF), the almost empty flag (AEF), and control the FIFO read enable (RD). Unlike SCAPI mode, the QCLK is not gated and is therefore continuous. Figure 26 shows the basic timing relationship of this mode.
PIXEL DATA
DV
CLKIN
QCLK
AFF
AEF
NOTES 1. THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT. 2. DV POLARITY IS SET BY THE PDV BIT.
Figure 25. SCAPI Output Mode FIFO Operation
DATA
RD
CLKIN
QCLK
AFF
AEF
THE POLARITY OF AFF AND AEF ARE CONTROLLED BY THE PFF BIT.
Figure 26. CAPI Output Mode FIFO Operation
REV. 0
-17-
ADV7185
Manual Clock Control
The ADV7185 offers several output clock mode options: the output clock frequency can be set by the input video line length, a fixed 27 MHz output, or by a user-programmable value. Information on the clock control register at 28h can be found in the register access map. When Bit 6 of this register (CLKMANE) is set to Logic "1," the output clock frequency will be determined by the user-programmable value (CLKVAL[15:0]). Using this mode, the output clock frequency is calculated as:
LLC = CLKVAL[17: 0] 220 x 28 x 3 x 27 MHz 16
For example, a required clock frequency of 25 MHz would yield a CLKVAL of 2D266h (184934).
Color Subcarrier Control
The color subcarrier manual frequency control register (CSMF[27:0]) can be used to set the DDFS block to a userdefined frequency. This function can be useful if the color subcarrier frequency of the incoming video signal is outside the standard FSC lock range. Setting Bit 4 reg 23h (CSM) to a Logic "1" enables the manual frequency control, the frequency of which will be determined by CSMF[27:0]. The value of CSMF[27:0] can be calculated as:
To control the device on the bus the following protocol must be followed. First the master initiates a data transfer by establishing a start condition, defined by a high to low transition on SDATA while SCLOCK remains high. This indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next 8 bits (7-Bit Address + R/W Bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDATA and SCLOCK lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic "0" on the LSB of the first byte means that the master will write information to the peripheral. A Logic "1" on the LSB of the first byte means that the master will read information from the peripheral. The ADV7185 acts as a standard slave device on the bus. The data on the SDATA pin is 8 bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7185 has 71 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis, without having to update all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLOCK high period, the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7185 will not issue an acknowledge and will return to the idle condition. If the user exceeds the highest subaddress in autoincrement mode, the following action will be taken: 1. In read mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDATA line is not pulled low on the ninth pulse. 2. In write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7185, and the part will return to the idle condition.
CSMF [27: 0] = FSC * x
*Required
228 27 MHz
MPU PORT DESCRIPTION
The ADV7185 supports a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. Two inputs, serial data (SDATA) and serial clock (SCLOCK), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7185 has two possible slave addresses for both read and write operations. These are unique addresses for the device and are illustrated in Figure 27. The LSB sets either a read or write operation. Logic Level "1" corresponds to a read operation while Logic Level "0" corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7185 to Logic Level "0" or Logic Level "1."
1 0 0 0 1 0 A1 X
ADDRESS CONTROL SET UP BY ALSB READ/WRITE CONTROL 0 1 WRITE READ
Figure 27. Slave Address
-18-
REV. 0
ADV7185
WRITE SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) DATA A(S) *** DATA A(S) P LSB = 0 READ SEQUENCE LSB = 1
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
S
SLAVE ADDR
A(S)
DATA
A(M)
***
DATA
A(M)
P
S = START BIT P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 28. Write and Read Sequences
SDATA
SCLOCK
S
1-7
8
9
1-7
8
9 ACK
1-7 DATA
8
9 ACK
P STOP
START ADDR R/W
ACK SUB ADDR
Figure 29. Bus Data Transfer
REV. 0
-19-
ADV7185
REGISTER ACCESSES REGISTER PROGRAMMING
The MPU can write to or read from all of the registers of the ADV7185 except the subaddress register, which is a write only register. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. Then a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.
The following section describes each register in terms of its configuration.
Subaddress Register (SR7-SR0)
The communications register is an 8-bit write only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place. Table II shows the various operations under the control of the subaddress register. Zero should always be written to SR7-SR6.
Register Select (SR5-SR0)
These bits are set up to point to the required starting address.
Table II. Subaddress Register
Register Name BASIC BLOCK Input Control Video Selection Video Enhancement Control Output Control Extended Output Control General-Purpose Output Reserved FIFO Control Contrast Control Saturation Control Brightness Control Hue Control Default Value Y Default Value C Temporal Decimation Power Management Status Register Info Register
Addr (Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
Register Name ADVANCED BLOCK Reserved Analog Control (Internal) Analog Clamp Control Digital Clamp Control 1 Digital Clamp Control 2 Shaping Filter Control Reserved Comb Filter Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Color Subcarrier Control 1 Color Subcarrier Control 2 Color Subcarrier Control 3 Color Subcarrier Control 4 Pixel Delay Control Manual Clock Control 1 Manual Clock Control 2 Manual Clock Control 3 Auto Clock Control AGC Mode Control Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 Manual Gain Shadow Control 1 Manual Gain Shadow Control 2 Misc Gain Control HSync Position Control 1 HSync Position Control 2 HSync Position Control 3 Polarity Control Reserved Reserved Reserved Reserved
Addr (Hex) 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 44 45 F1 F2
-20-
REV. 0
ADV7185
Table III. Basic Registers
Register Input Control Video Selection
Addr (Hex) 00 01
D7
D6
D5
D4
D3
D2 INSEL.2 SQPE YPM.2
D1 INSEL.1 VID QUAL.1 YPM.1
D0 INSEL.0 VID QUAL.0 YPM.0
VID SEL.3 VID SEL.2 VID SEL.1 VID SEL.0 INSEL.3 ASE BETACAM 4FSC COR.1 VBI EN BT656-4 HL_EN BL_C_VBI GPEH GPEL GP0.3 TOD OF SEL.3 OF SEL.2 DIFFIN COR.0 OF SEL.1
Video Enhancement 02 Control Output Control Extended Output Control General-Purpose Output Reserved FIFO Control Contrast Control Saturation Control Brightness Control Hue Control Default Value Y Default Value C Temporal Decimation 03 04 05 06 07 08 09 0A 0B 0C 0D 0E RES FFST CON.7 SAT.7 BRI.7 HUE.7 DEF Y.5 DEF C.7 AFR CON.6 SAT.6 BRI.6 HUE.6 DEF Y.4 DEF C.6 TDR.3 TRAQ FR CON.5 SAT.5 BRI.5 HUE.5 DEF Y.3 DEF C.5 TDR.2 PWRDN
OF SEL.O OM SEL.1 OMEL.O RANGE GP0.2 GP0.1 GP0.0
FFM.4 CON.4 SAT.4 BRI.4 HUE.4 DEF Y.2 DEF C.4 TDR.1 PS CG
FFM.3 CON.3 SAT.3 BRI.3 HUE.3 DEF Y.1 DEF C.3 TDR.0 PS REF
FFM.2 CON.2 SAT.2 BRI.2 HUE.2 DEF Y.0 DEF C.2 TDC.1 PDBP
FFM.1 CON.1 SAT.1 BRI.1 HUE.1
FFM.0 CON.0 SAT.0 BRI.0 HUE.0
DEF_ DEF_ AUTO_EN VAL_EN DEF C.1 TDC.0 PSC.1 DEF C.0 TDE PSC.0
Power Management 0F Status Register Info Register 10 11
STATUS.7 STATUS.6 STATUS.5 STATUS.4 STATUS.3 STATUS.2 STATUS.1 STATUS.0 IDENT.7 IDENT.6 IDENT.5 IDENT.4 IDENT.3 IDENT.2 IDENT.1 IDENT.0
Table IV. Advanced Registers
Register Reserved Reserved Analog Clamp Control Digital Clamp Control 1 Digital Clamp Control 2 Shaping Filter Control Reserved
Addr (Hex) 12 13 14 15 16 17 18
D7
D6
D5
D4
D3
D2
D1
D0
TIM_OE VCLEN DCCM DCC0.7 CSFM.2 DCT.1 DCC0.6 CSFM.1 DCT.0 DCC0.5 CSFM.0 CCLEN DCFE DCC0.4 YSFM.4 FACL.1 DCC0.11 DCC0.3 YSFM.3 FACL.0 DCC0.10 DCC0.2 YSFM.2 FICL.1 DCC0.9 DCC0.1 YSFM.1 FICL.0 DCC0.8 DCC0.0 YSFM.0
Comb Filter Control 19 Color Subcarrier Control 1 23
CCMB_AD CCM.1 CSM CSMF.27
CCM.0 CSMF.26 CSMF.25 CSMF.24
REV. 0
-21-
ADV7185
Table IV. Advanced Registers (continued)
Register Color Subcarrier Control 2 Color Subcarrier Control 3 Color Subcarrier Control 4 Pixel Delay Control Manual Clock Control 1 Manual Clock Control 2 Manual Clock Control 3 Auto Clock Control
Addr (Hex) 24 25 26 27 28 29 2A 2B
D7 CSMF.23 CSMF.15 CSMF.7 SWPC FIX27E
D6 CSMF.22 CSMF.14 CSMF.6
D5 CSMF.21 CSMF.13 CSMF.5 CTA.2
D4 CSMF.20 CSMF.12 CSMF.4 CTA.1
D3 CSMF.19 CSMF.11 CSMF.3 CTA.0
D2 CSMF.18 CSMF.10 CSMF.2
D1 CSMF.17 CSMF.9 CSMF.1
D0 CSMF.16 CSMF.8 CSMF.0
CLKMANE
CLKVAL. CLKVAL. 17 16
CLKVAL. CLKVAL. CLKVAL. CLKVAL. CLKVAL. CLKVAL. CLKVAL.9 CLKVAL.8 15 14 13 12 11 10 CLKVAL.7 CLKVAL.6 CLKVAL.5 CLKVAL.4 CLKVAL.3 CLKVAL.2 CLKVAL.1 CLKVAL.0 ACKLM.2 ACKLM.1 ACKLM.0 LAGC.2 CAGT.1 CMG.7 LAGT.1 LMG.7 SGUE LMGS.7 LMGS.6 CKE HSB.9 HSB.7 HSE.7 PHS HSB.8 HSB.6 HSE.6 PHVR FSC_INV HSE.9 HSB.5 HSE.5 PVS LMGS.5 LMGS.4 MIRE.2 HSE.8 HSB.4 HSE.4 PLLCR HSB.3 HSE.3 PF HSB.2 HSE.2 PDV HSB.1 HSE.1 PFF HSB.0 HSE.0 PCLK CAGT.0 CMG.6 LAGT.0 LMG.6 LMG.5 LMG.4 CMG.5 CMG.4 LAGC.1 LAGC.0 CMG.11 CMG.3 LMG.11 LMG.3 LMGS.11 LMGS.3 MIRE.1 CMG.10 CMG.2 LMG.10 LMG.2 LMGS.10 LMGS.2 MIRE.0 CAGC.1 CMG.9 CMG.1 LMG.9 LMG.1 LMGS.9 LMGS.1 AV_AL CAGC.0 CMG.8 CMG.0 LMG.8 LMG.0 LMGS.8 LMGS.10 PW_UPD
AGC Mode Control 2C Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 Manual Gain Shadow Control 1 Manual Gain Shadow Control 2 Misc Gain Control Hsync Position Control 1 Hsync Position Control 2 Hsync Position Control 3 Polarity Control Resample Control Reserved Reserved Reserved 2D 2E 2F 30 31 32 33 34 35 36 37 44 45 F1 F2
-22-
REV. 0
ADV7185
Table V. Input Control Register (Subaddress 00) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 0 0 INSEL[3:0]1 CVBS In on AIN12 0 0 0 1 CVBS In on AIN2 0 0 1 0 CVBS In on AIN3 0 0 1 1 CVBS In on AIN4 0 1 0 0 CVBS In on AIN5 0 1 0 1 CVBS In on AIN6 0 1 1 0 Y on AIN1, C on AIN43 0 1 1 1 Y on AIN2, C on AIN5 1 0 0 0 Y on AIN3, C on AIN6 1 0 0 1 Y on AIN1, U on AIN4, V on AIN54 1 0 1 0 Y on AIN2, U on AIN3, V on AIN6 0 0 0 0 Auto Detect PAL (BGHID), NTSC without VID_SEL[3:0]5 Pedestal 0 0 0 1 Auto Detect PAL (BGHID), NTSC (M) with Pedestal 0 0 1 0 Auto Detect PAL (N), NTSC (M) without Pedestal 0 0 1 1 Auto detect PAL (N), NTSC (M) with Pedestal 0 1 0 0 NTSC (M) without Pedestal 0 1 0 1 NTSC (M) with Pedestal 0 1 1 0 NTSC 4.43 without Pedestal 0 1 1 1 NTSC 4.43 with Pedestal 1 0 0 0 PAL BGHID without Pedestal 1 0 0 1 PAL N with Pedestal 1 0 1 0 PAL M without Pedestal 1 0 1 1 PAL M with Pedestal 1 1 0 0 PAL Combination N 1 1 0 1 PAL Combination N with Pedestal
NOTES 1 Allows the user to select an input channel as well as the input format. 2 Composite 3 S-Video 4 YUV 5 Allows the user to select the input video standard.
Table VI. Video Selection Register (Subaddress 01)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 1 0 VID_QUAL[1:0] 0 1 1 2 0 SQPE 1 3 0 DIFFIN 1 4 0 FFSC 1 BETACAM 0 1 RESERVED 0 6 1 ASE 0 Bit 0 0 1 0 1 Register Setting Broadcast Quality TV Quality VCR Quality Surveillance Quality Standard Mode Enable Square Pixel Mode Single-Ended Inputs Differential Inputs Standard Video Operation 5 Select 4 FSC Mode Standard Video Input Betacam Input Enable Set to Zero INSEL change will not cause reacquire. INSEL change will trigger reacquire.
NOTES 1 Allows the user to influence the time constant of the system depending on the input video quality. 2 Allows the user to enable/disable the square pixel operation. 3 Allows the user to select a differential input mode for every entry in the INSEL[3:0] table. 4 4 FSC Mode. Allows the selection of a special NTSC mode where the data is resampled to 4 FSC sampling rate. As a result the LLC will operate at a 4 FSC rate as well. Only valid for NTSC input. 5 NTSC only 6 Automatic Startup Enable. When set a change in the INSEL register will automatically be detected and lead the device to enter a video reacquire mode. May be disabled for genlocked video sources.
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Table VII. Video Enhancement Control Register (Subaddress 02)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 0 YPM[2:0]1 C = 4.5 dB, S = 9.25 dB2 0 0 1 C = 4.5 dB, S = 9.25 dB3 0 1 0 C = 4.5 dB, S = 5.75 dB 0 1 1 C = 1.25 dB, S = 3.3 dB 1 0 0 No Change; C = 0, S = 0 1 0 1 C = -1.25 dB, S = -3 dB 1 1 0 C = -1.75 dB, S = -8 dB 1 1 1 C = -3.0 dB, S = -8 dB 0 0 No Coring COR[1:0]4 0 1 Truncate if Y < black + 8 1 0 Truncate if Y < black + 16 1 1 Truncate if Y < black + 32 RESERVED 0 0 0 Set to Zero
NOTES 1 Y Peaking Filter Mode. Allows the user to boost/attenuate luma signals around the color subcarrier frequency. Used to enhance the picture and improve the contrast. 2 C = Composite (2.6 MHz) 3 S = S-Video (3.75 MHz) 4 Coring Selection. Controls optional coring of the Y output signal depending on its level.
Table VIII. Output Control Register (Subaddress 03)
Bit Description 1 OM_SEL[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 1 0 1 Bit 0 0 1 0 1 Register Setting Philips-Compatible Broktree API A-Compatible Broktree API B-Compatible Not Valid Setting 10-bit @ LLC 4:2:2 CCIR656 20-bit @ LLC2 4:2:2 CCIR656 16-bit @ LLC2 4:2:2 CCIR656 8-bit @ LLC 4:2:2 CCIR656 12-bit @ LLC2 4:1:1 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Drivers Dependent on OE Pin Drivers Three-Stated Regardless of OE Pin All Lines Filtered and Scaled Active Video Region Only
OF_SEL[3:0] 2
TOD 3 VBI_EN
4
NOTES 1 Output Mode Selection. Selects the output mode as in the timing and interface type. 2 Allows the user to choose from a set of output formats. 3 Three-State Output Drivers. Allows the user to three-state the output drivers regardless of the state of the OE pin. 4 Allows VBI data (lines 1 to 21) to be passed through with only a minimum amount of filtering performed.
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Table IX. Extended Output Control Register (Subaddress 04)
Bit Description 1 RANGE RESERVED 2 DDOS[2:0] 4 BT656-4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 1 1 0 0 0 0 0 1
Register Setting CCIR-Compliant Fill Whole Accessible Range No Additional Data BT656-3-Compatible BT656-4-Compatible
3
NOTES 1 Allows the user to select the range of output values. Can be CCIR601-compliant or fill the whole accessible number range. 2 D Data Output Selection. If the 100-pin package is used, the 12 additional pins can output additional data. 3 12 Pins Three-State 4 Allows the user to select an output mode that is compatible with BT656-4 or BT656-3.
Table X. General-Purpose Output Register (Subaddress 05)
Bit Description GPO[3:0] GPEL
2 1
GPEH
3
BL_C_VBI HL_EN
5, 6
4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 0 0 User Programmable Pixel Data Valid Off 0 GPO[1:0] Three-Stated 1 GPO[1:0] Enabled 0 GPO[3:2] Three-Stated 1 GPO[3:2] Enabled 0 Decode and Output Color During VBI 1 Blank Cr and Cb Data During VBI 0 GPO[0] Pin Function 1 GPO[0] Shows HLOCK Status
NOTES 1 Pixel Data Valid Off. These general-purpose output pins may be programmed by the user but are only available in selected output modes OF_SEL[3:0] and when the output drivers are enabled using GPEL, GPEH, and HL_Enable bits. 2 General-Purpose Enable Low. Enables the output drivers for the general-purpose outputs Bits 0 and 1. 3 General-Purpose Enable High. Enables the output drivers for the general-purpose outputs Bits 2 and 3. 4 Blank Chroma during VBI. 5 Hlock Enable. This bit causes the GPO[0] pin to output Hlock instead of GPO[0]. Only available in certain output modes. 6 GPO lower bits must be enabled GPEL. Disabled.
Table XI. FIFO Control Register (Subaddress 07)
Bit Description 1 FFM[4:0] 2 FR AFR
4
FFST
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 1 0 0 0 1 0 1 0 1
Register Setting User-Programmable Normal Operation 3 FIFO Reset No Auto Reset Auto Reset Synchronous to CLKIN Synchronous to 27 MHz
NOTES 1 FIFO Flag Margin. Allows the user to program the location at which the FIFO flags AEF and AFF. 2 FIFO Reset. Setting this bit will cause the FIFO to reset. 3 Bit is auto-cleared. 4 Automatic FIFO Reset. Setting this bit will cause the FIFO to automatically reset at the end of each field of video. 5 FIFO Flag Self Time. Sets whether the FIFO flags AEF, AFF, and HFF are output synchronous to the external CLKIN of the 27 MHz internal clock.
Table XII. Contrast Register (Subaddress 08)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CON[7:0]* 1 0 0 0 0 0 0 0
*Contrast Adjust. This is the user control for contrast adjustment.
REV. 0
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Table XIII. Saturation Register (Subaddress 09) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting SAT[7:0]* 0 0 0 0 0 0 0 0 -42 dB 1 0 0 0 0 0 0 0 0 dB 1 1 1 1 1 1 1 1 6 dB
*Saturation Adjust. Allows the user to adjust the saturation of color output.
Table XIV. Brightness Register (Subaddress 0A) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting BRI[7:0]* 0 0 0 0 0 0 0 0 0 dB 0 1 1 1 1 1 1 1 3 dB 1 0 0 0 0 0 0 0 -3 dB
*Controls the brightness of the video signal. Range = 3 dB.
Table XV. Hue Register (Subaddress 0B) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting HUE[7:0]* 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 90 1 0 0 0 0 0 0 0 -90
*Contains the value for the color hue adjustment. Range = 90.
Table XVI. Default Value Y Register (Subaddress 0C) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 DEF_ VAL_ EN1 Use Programmed Value2 1 Use Default Value 0 DEF_ VAL_ Use Programmed Value4 1 Use Default Value AUTO_EN3 0 0 0 1 0 0 DEF_Y[5:0]5
NOTES 1 Default Value Enable 2 Y, Cr, and Cb Values 3 Default Value Auto Enable. In the case of lost lock enables/disables default values. 4 When lock is lost. 5 Default Value Y. Holds the Y default value.
Table XVII. Default Value C Register (Subaddress 0D)
Bit Description DEF_C[7:0]* Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 1 0 0 0 Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0} 1 0 0 0 Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}
*Default Value C. Cr and Cb default values are defined in this register.
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Table XVIII. Temporal Decimation Register (Subaddress 0E)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 Disabled TDE1 1 Enabled 0 0 Suppress Frames; Start with Even Field TDC[1:0]2 0 1 Suppress Frames; Start with Odd Field 1 0 Suppress Even Fields Only 1 1 Suppress Odd Fields Only 0 0 0 0 Skip None TDR[3:0]3 0 0 0 1 Skip 1 Field/Frame 0 0 1 0 Skip 2 Fields/Frames 0 0 1 1 Skip 3 Fields/Frames 0 1 0 0 Skip 4 Fields/Frames 0 1 0 1 Skip 5 Fields/Frames 0 1 1 0 Skip 6 Fields/Frames 0 1 1 1 Skip 7 Fields/Frames 1 0 0 0 Skip 8 Fields/Frames 1 0 0 1 Skip 9 Fields/Frames 1 0 1 0 Skip 10 Fields/Frames 1 0 1 1 Skip 11 Fields/Frames 1 1 0 0 Skip 12 Fields/Frames 1 1 0 1 Skip 13 Fields/Frames 1 1 1 0 Skip 14 Fields/Frames 1 1 1 1 Skip 15 Fields/Frames RESERVED 0 Set to Zero
NOTES 1 Temporal Decimation Enable. Allows the user to enable/disable the temporal function. Configured using TDC[1:0] and TDR[3:0]. 2 Temporal Decimation Control. Allows the user to select the suppression of selected fields of video. 3 Temporal Decimation Rate. Specifies how many fields/frames to be skipped before a valid one is output. As specified in the TDC[1:0] register.
Table XIX. Power Management Register (Subaddress 0F) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 Full Operation PSC[1:0]1 0 1 CVBS Input Only 1 0 Digital Only 1 1 Power Save Mode 0 Power-Down Controller by Pin PDBP2 1 Power-Down Controller by Bit 0 Reference Functional PS_REF3 1 Reference in Power Save Mode 0 Clock Generator Functional PS_CG4 1 CG in Power Save Mode 0 System Functional PWRDN 5 1 Power-Down 0 Normal Operation TRAQ6 1 Require Video Signal 0 RESET7 1 Resets Digital Core and I2C
NOTES 1 Power Save Control. Allows a set of different power save modes to be selected. 2 Power-Down Bit Priority. There are two ways to shut down the digital core; the Power-Down Bit sets which has higher priority. 3 Power Save Reference. Allows the user to enable/disable the internal analog reference. 4 Power Save for the LLC Clock Generator 5 Power-Down. Disables the input pads and powers down the 27 MHz clock. 6 Timing Reacquire. Will cause the part to reacquire the video signal and is the software version of the ISO pin. If bit is set will clear itself on the next 27 MHz clock cycle. 7 Resets Digital Core and I 2C; self-clearing bit.
REV. 0
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Table XX. Status Register1 (Subaddress 10)
Bit Description 2 STATUS[7:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Register Setting In Lock (current) Lost Lock (since last read) FSC Locked (current) 50 Hz Field Rate Auto Detected ADC Underflow Detected ADC Overflow Detected White Peak Active Color Kill Active
NOTES 1 Read only 2 Provides information about the internal status of the decoder.
Table XXI. Info Register1 (Subaddress 11) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting X X X X X X X X 0 = v85a, 3 = v85b, 4 = v85b3 IDENT[7:0]2
NOTES 1 Read only 2 Provides identification on the revision of the part.
Table XXII. Analog Control Internal Register (Subaddress 13)
Bit Description TIM_OE * RESERVED
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 0 0 0 1 1
Register Setting Dependent on OE and TOD HS, VS, F Forced Active Set at Default Value
*Timing Signals Output. Enables the user to force the output drivers for H-SYNC,V-SYNC, and Field into an active state regardless of the OE pin and TOD bit.
Table XXIII. Analog Clamp Control Register (Subaddress 14) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 I On for 16 Clock Cycles FICL[1:0]1 0 1 I On for 32 Clock Cycles 1 0 I On for 64 Clock Cycles 1 1 I On for 128 Clock Cycles 0 0 I On for 16 Clock Cycles FACL[1:0]2 0 1 I On for 32 Clock Cycles 1 0 I On for 64 Clock Cycles 1 1 I On for 128 Clock Cycles 0 I Sources Switched Off CCLEN 3 1 I Sources Enabled 0 Voltage Clamp Disabled VCLEN 4 1 Voltage Clamp Enabled RESERVED 0 0 Set to Zero
NOTES 1 Fine Clamp Length. Controls the number of clock cycles for which the slow current is on. 2 Fast Clamp Length. Controls the number of clock cycles for which the fast current is on. 3 Current Clamp Enable. Allows the user to switch off the I sources in the analog front end. 4 Voltage Clamp Enable. Allows the user to disable the voltage clamp circuitry.
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Table XXIV. Digital Clamp Control 1 Register (Subaddress 15) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting X X X X Only applicable if DCCM is set to manual offset DCCO[11:8]1 mode. 0 Digital Clamp Operational DCFE 2 1 Digital Clamp Frozen 0 0 Slow (TC = 1 second) DCT[1:0]3 0 1 Medium (TC = 0.5 second) 1 0 Fast (TC = 0.1 second) 1 1 Dependent on VID_QUAL 0 Automatic Digital Clamp DCCM[7:0]4 1 Manual Offset Correction
NOTES 1 (Digital Color Clamp Offset) Holds upper 4 bits of the digital offset value which is added to the raw data from the ADC before entering the core. 2 (Digital Clamp Freeze Enable) Allows the user to freeze the digital clamp loop at any point in time. 3 (Digital Clamp Timing) Determines the time constant of the digital clamping circuitry. 4 (Digital Color Clamp Mode) Sets the mode of operation for the digital clamp circuitry. Offset correction via DCCO for C only.
Table XXV. Digital Clamp Control 2 Register (Subaddress 16)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting DCCO[7:0]* X X X X X X X X
*Digital Color Clamp Offset. Holds the lower 8 bits of the digital offset value which is added to the raw data from the ADC before entering the core. Only applicable if DCCM is set to manual offset mode.
Table XXVI. Shaping Filter Control Register (Subaddress 17)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 0 0 0 Auto Wide Notch YSFM[4:0]1 0 0 0 0 1 Auto Narrow Notch 0 0 0 1 0 SVHS 1 - - - - - - 1 0 0 1 0 SVHS 17 1 0 0 1 1 PAL NN1 1 0 1 0 0 PAL NN2 1 0 1 0 1 PAL NN3 1 0 1 1 0 PAL WN 1 1 0 1 1 1 PAL WN 2 1 1 0 0 0 NTSC NN1 1 1 0 0 1 NTSC NN2 1 1 0 1 0 NTSC NN3 1 1 0 1 1 NTSC WN1 1 1 1 0 0 NTSC WN2 1 1 1 0 1 NTSC WN3 1 1 1 1 0 Not Used 1 1 1 1 1 SVHS 18 0 0 0 Auto Selection 1.5 MHz CSFM[2:0]2 0 0 1 Auto Selection 2.17 MHz 0 1 0 SH1 - - - - 1 1 0 SH5 1 1 1 SH6
NOTES 1 Y Shaping Filter Mode. Allows the user to select a wide range of low-pass and notch filters. 2 C Shaping Filter Mode. Allows the selection from a range of low-pass chrominance filters. Auto = filter selected based on scaling factor.
REV. 0
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ADV7185
Table XXVII. Comb Filter Control Register (Subaddress 19) Bit Description RESERVED CCM[1:0]1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 0 0 0 0 0 1 1 0 1 Bit 2 Bit 1 Bit 0 0 0 0 1 0 1 Register Setting Set to Zero No Comb 1H 2H Not Valid, Do Not Use Chroma Comb Nonadaptive Chroma Comb Adaptive
CCMB_AD 2
NOTES 1 Chroma Comb Mode. Selects a primary mode for the filter. 2 Chroma Comb Adaptive
Table XXVIII. Color Subcarrier Control 1 Register (Subaddress 23) Bit Description 1 CSMF[27:24] 2 CSM RESERVED Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X 0 1 1 1 1 Register Setting Manual FSC Disabled 3 User-Defined FSC Set to One
NOTES 1 Color Subcarrier Manual Frequency. Holds the value used to enable the user to support odd subcarrier frequencies. 2 Color Subcarrier Manual 3 Defined in CSFM[27:0]
Table XXIX. Color Subcarrier Control 2 Register (Subaddress 24)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CSMF[23:16]* X X X X X X X X
*Color Subcarrier Manual Frequency. Holds the value used to enable the user to support odd subcarrier frequencies.
Table XXX. Color Subcarrier Control 3 Register (Subaddress 25)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CSMF[15:8]* X X X X X X X X
*Color Subcarrier Manual Frequency. Holds the value used to enable the user to support odd subcarrier frequencies.
Table XXXI. Color Subcarrier Control 4 Register (Subaddress 26)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CSMF[7:0]* X X X X X X X X
*Color Subcarrier Manual Frequency. Holds the value used to enable the user to support odd subcarrier frequencies.
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ADV7185
Table XXXII. Pixel Delay Control Register (Subaddress 27)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 0 0 0 Set to Zero 0 0 0 Not Valid CTA[2:0]1 0 0 1 Chroma + 2 Pixel (Early) 0 1 0 Chroma + 1 Pixel (Early) 0 1 1 No Delay 1 0 0 Chroma - 1 Pixel (Late) 1 0 1 Chroma - 2 Pixel (Late) 1 1 0 Chroma - 3 Pixel (Late) 1 1 1 Not Valid RESERVED 1 Set to One 0 No Swapping SWPC2 1 Swap the Cr and Cb Values
NOTES 1 Chroma Timing Adjust. Allows a specified timing difference between the luma and chroma samples. 2 Allows the Cr and Cb samples to be swapped.
Table XXXIII. Manual Clock Control 1 Register (Subaddress 28) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting X X CLKVAL[17:16]1 RESERVED 1 1 1 1 Set to Default 0 Output Frequency Set by Video CLKMANE 2 1 Frequency Set by CLKVAL[17:0] 0 Output Frequency Set by Clock Generator FIX27E3 1 Output 27 MHz Fixed
NOTES 1 If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins. 2 Clock Generator Manual Enable. Allows the analog clock generator to produce a fixed clock frequency that is not dependent on the video signal. 3 Allows the o/p of fixed 27 MHz crystal clock via LLC, LLC2, and LLCR EF o/p pins.
Table XXXIV. Manual Clock Control 2 Register (Subaddress 29)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CLKVAL[15:8]* X X X X X X X X
*If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
Table XXXV. Manual Clock Control 3 Register (Subaddress 2A)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CLKVAL[7:0]* X X X X X X X X
*If enabled via CLKMANE, CLKVAL[17:0] determines the fixed output frequency. On the LLC, LLC2, and LLCREF pins.
REV. 0
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ADV7185
Table XXXVI. Auto Clock Control Register (Subaddress 2B)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 0 0 0 0 0 Set to Zero ACLKN[2:0]* 0 0 0 Color Burst Line 0 0 1 Start Line 24 Color Burst Line 0 1 0 Active Video 0 1 1 Active Video (<304) PAL, (<264) NTSC 1 0 0 Active Video (<304) PAL, (<256) NTSC 1 0 1 Active Video (<319/320) PAL, (<273/274) NTSC 1 1 1 1 0 1 Invalid Invalid
*Automatic Clock Generator Mode. Influences the mode of operation for the LLC. Only when not in Manual Mode.
Table XXXVII. AGC Mode Control Register (Subaddress 2C)
Bit Description 1 CAGC[1:0]
RESERVED LAGC[2:0] 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 0 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1
Bit 0 0 1 0 1
RESERVED
1
Register Setting Manual Fixed Gain. Use CMG [11:0] Use Luma Gain for Chroma Automatic Gain. Based on color burst Freeze Chroma Gain Set to One 3 Manual Fixed Gain AGC No Override through White Peak; Man IRE 4 Control AGC Auto Override through White Peak; Man 4 IRE Control AGC No Override through White Peak; Man IRE 4 Control AGC Auto Override through White Peak; Man 4 IRE Control AGC Active Video with White Peak AGC Active Video with Average Video Freeze Gain Set to One
NOTES 1 Chroma Automatic Gain Control. Selects the basic mode of operation for the AGC in the chroma path. 2 Luma Automatic Gain Control. Selects the mode of operation for the gain control in the luma path. 3 Use LMG[11:0]. 4 Blank level to sync tip.
Table XXXVIII. Chroma Gain Control 1 Register (Subaddress 2D) Bit Description 1 CMG[11:8] RESERVED 2 CAGT[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X 1 1 0 0 0 1 1 0 1 1 Register Setting Set to One Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Dependent on VID_QUAL
NOTES 1 Chroma Manual Gain. Can be used to program a desired manual chroma gain or read back the actual used gain value. CAGC[1:0] settings will decide in which mode CMG[11:0] will operate. 2 Chroma Automatic Gain Timing. Allows adjustment of the Chroma AGC tracking speed. Will only have effect if CAGC[1:0] is set to auto gain (10b).
Table XXXIX. Chroma Gain Control 2 Register (Subaddress 2E)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting CMG[7:0]* X X X X X X X X
*Chroma Manual Gain. Lower 8 bits, see CMG [11:8] for description.
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Table XL. Luma Gain Control 1 Register (Subaddress 2F) Bit Description 1 LMG[11:8] RESERVED 2 LAGT[1:0] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X X X 1 1 0 0 0 1 1 0 1 1 Register Setting Set to One Slow (TC = 2 sec) Medium (TC = 1 sec) Fast (TC = 0.2 sec) Dependent on VID_QUAL
NOTES 1 Luma Manual Gain. Can be used to program a desired manual chroma gain or read back the actual used gain value. LAGC[1:0] settings will decide in which mode LMG[11:0] will operate. 2 Luma Automatic Gain Timing. Allows adjustment of the Luma AGC tracking speed. Will only have effect if LAGC[1:0] is set to auto gain (10b).
Table XLI. Luma Gain Control 2 Register (Subaddress 30)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting LMG[7:0]* X X X X X X X X
*Luma Manual Gain. Can be used program a desired manual chroma gain or read back the actual used gain value.
Table XLII. Manual Gain Shadow Control 1 Register (Subaddress 31)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting X X X X LMGS[11:8]1 RESERVED 1 1 1 Set to One 0 Disable LMGS Update SGUE 2 1 Use LMGS Update Facility
NOTES 1 Luma Manual Gain Store. Has dual functions; a desired manual luma gain can be programmed or a readback from the register will return the actual gain used. Gain value will only become active when LAGC[2:0] set to manual fixed gain. The function and readback value are dependent on LAGC[2:0] setting. 2 Surveillance Gain Update Enable. Enables surveillance mode operation (see LMGS[11:0] for details).
Table XLIII. Manual Gain Shadow Control 2 Register (Subaddress 32)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting LMG[7:0]* X X X X X X X X
*Chroma Manual Gain. Lower 8 bits, see LMG[11:8] for description.
Table XLIV. Miscellaneous Gain Control Register (Subaddress 33)
Bit Description 1 PW_UPD AV_AL
2
MIRE[2:0]
3
RESERVED CKE 4 RESERVED
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1
Register Setting Update Gain Once per Line Update Gain Once per Field Lines 33 to 310 Lines 33 to 270 PAL-133 NTSC-122 PAL-125 NTSC-115 PAL-120 NTSC-110 PAL-115 NTSC-105 PAL-110 NTSC-100 PAL-105 NTSC-100 PAL-100 NTSC-100 PAL-100 NTSC-100 Set to One Color Kill Disabled Color Kill Enabled Set to One
NOTES 1 Peak White Update. Determines the gain based on measurements taken from the active video; this bit determines the rate of gain change. LAGC[1:0] must be set to the appropriate mode to enable peak white or average video in the first case. 2 Average Brightness Active Lines. Allows the selection between two ranges of active video to determine the average brightness. 3 Max IRE. Sets the max I/p IRE level depending on the video standard. 4 Color Kill Enable. Allows the optional color kill function to be switched on or off.
REV. 0
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ADV7185
Table XLV. HSync Position Control 1 Register (Subaddress 34) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 1 1 1 1 Set to One 0 0 HSync ends after HSE[9:0] pixel after falling edge HSE[9:8]1 of HSync. 0 0 HSync starts after HSB[9:0] pixel after the falling HSB[9:8]2 edge of HSync.
NOTES 1 HSync End. Allows the positioning of the HSync output within the video line. 2 HSync Begin. Allows the positioning of HSync output within the video line.
Table XLVI. HSync Position Control 2 Register (Subaddress 35) Bit Description HSB[7:0]1
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 0 0 0 0 0 1
Using HSB[9:0] and HSE[9:0] the user can program the position and length of HSync output signal.
Table XLVII. HSync Position Control 3 Register (Subaddress 36)
Bit Description HSE[7:0]1
1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 0 0 0 0 0 0 0
Using HSB[9:0] and HSE[9:0] the user can program the position and length of HSync output signal.
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Table XLVIII. Polarity Register (Subaddress 37)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting 0 Active High PCLK 1 1 Active Low 0 Active High PFF2 1 Active Low 0 Active High PDV3 1 Active Low 0 Active High PF4 1 Active Low 0 Active High PLLCR 5 1 Active Low 0 Active High PVS6 1 Active Low 0 Active High PHVR7 1 Active Low 0 Active High PHS8 1 Active Low
NOTES 1 Sets the polarity of LLC, LLC2, and QClk. 2 Sets the polarity of HFF, AEF, and AFF. 3 Sets the polarity for Data Field. 4 Sets the field sync polarity. 5 Sets the LLCREF polarity. 6 Sets the VSync polarity. 7 Sets the HREF and VREF sync polarities. 8 Sets HSync polarity.
REV. 0
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ADV7185
Table XLIX. Resample Control Register (Subaddress 44)
Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting RESERVED 0 0 0 0 0 1 Set to Default FSC_INV* X NB No Default Value 0 Compatible with ADV7190, ADV7191, and ADV7194 1 Compatible with ADV717x RESERVED 0 Set to Zero
*Color Subcarrier RTCO Inversion. Allows the inversion of the GL bit.
Table L. Reserved (Subaddress 45) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reserved 0 0 1 X X 0 1 1 Default Values Functions 1 0 1 1 1 0 1 1 Set to These Values
Table LI. Reserved (Subaddress F1) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reserved 1 1 1 1 0 1 1 X Default Values Functions 1 1 1 0 1 1 1 1 Set to These Values
Table LII. Reserved (Subaddress F2) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting Reserved 1 0 0 1 1 1 0 X Default Values Functions 1 0 0 0 0 0 0 0 Set to These Values
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ADV7185
Table LIII. Power-On Reset Values for MPU Registers
Register BASIC BLOCK Input Control Video Selection Video Enhancement Control Output Control Extended Output Control General-Purpose Output Reserved FIFO Control Contrast Control Saturation Control Brightness Control Hue Control Default Value Y Default Value C Temporal Decimation Power Management Status Register Info Register
Addr (Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11
Default (Hex) 00 80 04 0C 0C 40 XX 04 80 80 0 0 10 88 00 00
Register ADVANCED BLOCK Reserved Analog Control (Internal) Analog Clamp Control Digital Clamp Control 1 Digital Clamp Control 2 Shaping Filter Control Reserved Comb Filter Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Color Subcarrier Control 1 Color Subcarrier Control 2 Color Subcarrier Control 3 Color Subcarrier Control 4 Pixel Delay Control Manual Clock Control 1 Manual Clock Control 2 Manual Clock Control 3 Auto Clock Control . AGC Mode Control Chroma Gain Control 1 Chroma Gain Control 2 Luma Gain Control 1 Luma Gain Control 2 Manual Gain Shadow Control 1 Manual Gain Shadow Control 2 Miscellaneous Gain Control Hsync Position Control 1 Hsync Position Control 2 Hsync Position Control 3 Polarity Control Reserved Reserved Reserved Reserved
Addr (Hex) 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 44 45 F1 F2
Default (Hex) XX 45 18 6X XX 01 XX 10 XX XX XX XX XX XX XX XX XX EX XX XX XX 58 XX XX XX A0 CE FX XX FX XX 7X XX E3 0F 01 00 00 X1 XX FX 9X
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ADV7185 Appendix
BOARD DESIGN AND LAYOUT CONSIDERATIONS Supply Decoupling
The ADV7185 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed and accurate performance are achieved. Figure 30 shows the recommended analog circuit layout. The layout should be optimized for lowest noise on the ADV7185 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VDD and GND pins should be minimized to reduce inductive ringing.
Ground Planes
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of power pins on the ADV7185 must have at least one 0.1 F decoupling capacitor to its corresponding ground. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7185 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high-frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The ground plane should be split into two, one analog and one digital. They should be joined directly under the ADV7185. The analog ground return path should be through the digital (the digital ground is connected to the analog ground and also the system ground, whereas the analog ground is only connected to the digital ground; this will ensure only analog current will flow in the analog ground).
Power Planes
The digital inputs and outputs to and from the ADV7185 should be isolated as much as possible from the analog inputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to and from the ADV7185 should be avoided to reduce noise pickup. Any series termination resistors (typically 33R) for the digital inputs should be connected to the high speed digital outputs.
Analog Signal Interconnect
The ADV7185 and any associated analog circuitry should have its own power planes, referred to as the analog and digital power planes. These power planes should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7185. The PCB power plane should provide power to all digital logic on the PC board and the digital power pins on the ADV7185, and the analog power plane should provide power to all analog power pins on the ADV7185. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged so the plane-to-plane noise is common-mode.
The ADV7185 should be located as close as possible to the input connectors to minimize noise pickup and reflections due to impedance mismatch. The video input signals should overlay the ground plane, and not the analog power plane, to maximize the high-frequency power supply rejection. Digital outputs, especially pixel data Inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. The ADV7185 should have no inputs left floating. Any inputs that are not required should be tied to ground.
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ADV7185
FERRITE BEAD AVDD 33 F AVSS FERRITE BEAD AVSS DVSS DVDD 33 F DVSS AIN1 100nF AIN2 100nF AIN3 100nF AIN4 100nF AIN5 100nF AIN6 10 F DVSS 100nF DVDDIO DVDD AIN1 AVSS1 AIN2 AVSS2 AIN3 AVSS3 AIN4 AVSS4 AIN5 AVSS5 AIN6 AVSS6 AVDD GPO[0]/P0 GPO[1]/P1 P2 P3 P4 P5 P6 P7 P8 P9 GPO[2]/P10 GPO[3]/P11 P12 P13 P14 P15 P16 P17 P18 P19 LLC LLC2 LLCREF CAPC1 0.1 F 10 F 0.1 F CAPC2 AEF AFF RD OE DV GL/QCLK/HFF PWRDN HS/RESET VS/RESET FIELD XTAL 33 F 27MHz DVSS DVSS XTAL1 33 F AVDD DVDD 2k I2C INTERFACE CONTROL LINE I2C INTERFACE CONTROL LINE 2k 100R SCLK 100R SDA RESET 100nF RESET *P19-P12: 8-BIT CCIR656 PIXEL DATA @ 27MHz P19-P10: 10-BIT EXTENDED CCIR656 PIXEL DATA @ 27MHz P9-P2: Cb AND Cr 16-BIT CCIR656 PIXEL DATA @ 13.5MHz P19-P12: Y1 AND Y2 16-BIT CCIR656 PIXEL DATA @ 13.5MHz P9-P0: Cb AND Cr 20-BIT EXTENDED CCIR656 PIXEL DATA @ 13.5MHz P19-P10: Y1 AND Y2 20-BIT EXTENDED CCIR656 PIXEL DATA @ 13.5MHz DVDD DVSS ALSB 2nF ELPF 5.6k 68pF ALMOST EMPTY FIFO O/P ALMOST FULL FIFO O/P READ SIGNAL I/P OUTPUT ENABLE I/P DATA VALID O/P GL/QCLK/HFF O/P FIFO MANAGEMENT SIGNALS ONLY USED IN FIFO MODE; USE LLC AND GENLOCK FOR NON-FIFO MODE 27MHz OUTPUT CLOCK 13.5MHz OUTPUT CLOCK CLOCK REFERENCE O/P 0.1 F DVSS 0.01 F DVSS POWER SUPPLY DECOUPLING FOR EACH POWER PIN 10 F AVSS 0.1 F AVSS 0.01 F AVSS POWER SUPPLY DECOUPLING FOR EACH POWER PIN
MULTIFORMAT PIXEL PORT*
AVSS INPUT SWITCH OVER
AVSS
AVSS
AVSS
AVSS
AVSS ISO
0.1 F CAP Y1 0.1 F 10 F 0.1 F CAP Y2
AVSS AVSS 0.1 F
AVSS AVSS CML 0.1 F REFOUT 10 F 0.1 F
POWER-DOWN INPUT HS/RESET O/P VS/RESET O/P FIELD O/P
DVDD
AVSS
4.7k DVDD
DVSS
Figure 30. Recommended Analog Circuit Layout
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ADV7185
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches)
80-Lead Thin Plastic Quad Flatpack [LQFP] (ST-80)
16.25 (0.6398) SQ 15.75 (0.6201) 1.60 (0.0630) MAX 0.75 (0.0295) 0.50 (0.0197) SEATING PLANE 14.05 (0.5532) SQ 13.95 (0.5492)
80 1 61 60
TOP VIEW
(PINS DOWN)
12.35 (0.4862) TYP SQ
COPLANARITY 0.10 (0.0039) MAX 0.15 (0.0059) 0.05 (0.0020) 1.45 (0.0571) 1.35 (0.0531)
20 21
41 40
0.73 (0.0287) 0.57 (0.0224)
0.35 (0.0138) 0.25 (0.0098)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
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REV. 0
PRINTED IN U.S.A.
C01677-0-5/02(0)
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